1. Field of the Invention
The present invention relates to a method for planarizing conducting layers for a semiconductor device, and in particular, to a method for planarizing metal or metal-silicide layers used for interconnect layers between the active or passive elements in a semiconductor integrated circuit.
2. Description of the Prior Art
In a semiconductor integrated circuit, a plurality of active or passive elements in a semiconductor substrate are electrically interconnected to each other using conducting layers such as a layer of aluminum compound metal with copper and silicon. These conducting layers are usually formed by means of vacuum evaporation or sputtering, whereby the deposited layers generally have poor step-coverage. This results in frequent disconnection of interconnect layers in subsequent thermal processes. The disconnection problem becomes increasingly significant for higher density of semiconductor integrated circuits. This problem could be solved by planarizing the deposited conducting layers. In an attempt to eliminate poor step-coverage and thus minimize this problem, a technique has been developed for planarizing the deposited conducting layers by heating and melting them for mass-flow as shown in FIGS. 1 (a) and (b), which is described in Japanese Unexamined Patent (Kokai) No. S63-236345. FIG. 1(a) shows a cross-sectional view of a semiconductor integrated circuit, particularly, an as-deposited conducting layer 54 on a via hole 53 formed in an insulated layer 52 on a semiconductor substrate 51, having poor step-coverage especially on the side-walls. FIG. 1(b) also shows a cross sectional view of a planarized conducting layer 54S by melting it to flow into a via hole 53, achieving a perfect planarity of the surface with a conducting plug in a steep via hole. The term "a via hole" as used herein is intended to include a vertical hole which connects the single crystal and polysilicon of the active areas of a device to a first layer of conducting material, and which connects a first layer of conducting material to a second layer of conducting material, second a to third, a etc. A conducting layer deposited to crossover an insulated interconnect already deposited and patterned on another insulating layer is also simultaneously planarized but is not as shown. However, in the conventional planarizing process, completion of planarization can be recognized only by observing surfaces of a conducting layer after heating is completely terminated. The optimum heating condition is usually determined after several trials by changing both temperature and time for heating. The problem is that a discrepancy in temperature between conducting layer surfaces and the substrate due to a time-lag in thermal conduction leads to excess or insufficiency of heating which often results in coagulation of a molten conducting layer as liquid droplets or even evaporation, or in contrast, failing to planarize it because of non-melting. In either ease, lack of stability in the planarizing process degrades reliability of interconnects of high-density semiconductor integrated circuits. Thus one of the major advantages of the thermal planarizing process is severely compromised.